Главное Интегральные схемы (ИС) Встраиваемые - FPGA (Полевые программируемые вентильные матрицы) EP610DC-30
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Спецификация Часто задаваемые вопросы
- Surface Mount:NO
- Number of Pins:24
- Number of I/Os:16
- Operating Temperature (Max.):70°C
- JESD-609 Code:e0
- Pbfree Code:no
- Number of Terminations:24
- ECCN Code:EAR99
- Terminal Finish:Tin/Lead (Sn/Pb)
- Additional Feature:MACROCELLS INTERCONNECTED BY GLOBAL BUS; 16 MACROCELLS; 2 EXTERNAL CLOCKS
- HTS Code:8542.39.00.01
- Terminal Position:DUAL
- Terminal Form:THROUGH-HOLE
- Peak Reflow Temperature (Cel):NOT SPECIFIED
- Supply Voltage:5V
- Terminal Pitch:2.54mm
- Time@Peak Reflow Temperature-Max (s):NOT SPECIFIED
- Pin Count:24
- Number of Outputs:16
- Qualification Status:Not Qualified
- Supply Voltage-Max (Vsup):5.25V
- Power Supplies:5V
- Temperature Grade:COMMERCIAL
- Supply Voltage-Min (Vsup):4.75V
- Clock Frequency:33.3MHz
- Propagation Delay:32 ns
- Architecture:PAL-TYPE
- Organization:4 DEDICATED INPUTS, 16 I/O
- Programmable Logic Type:UV PLD
- Output Function:MACROCELL
- Number of Dedicated Inputs:4
- Number of Product Terms:160
- RoHS Status:RoHS Compliant
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